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| 1 for more information www.linear.com/ltc3769 n industrial n automotive n medical n military typical a pplica t ion n synchronous operation for highest efficiency and reduced heat dissipation n wide v in range: 4.5v to 60v (65v abs max); operates down to 2.3v after start-up n output voltage up to 60v n 1% 1.200v reference voltage n r sense or inductor dcr current sensing n 100% duty cycle capability for synchronous mosfet n low quiescent current: 28a n phase-lockable frequency (75khz to 850khz) n programmable fixed frequency (50khz to 900khz) n power good output voltage monitor n low shutdown current: 4a n internal ldo powers gate drive from vbias or extv cc n thermally enhanced low profile 24-pin 4mm 4mm qfn package and 20-lead tssop package fea t ures descrip t ion 60v low i q synchronous boost controller the lt c ? 3769 is a high performance single output syn - chronous boost converter controller that drives an all n-channel power mosfet stage. synchronous rectifica- tion increases efficiency, reduces power losses and eases thermal requirements, simplifying high power boost ap - plications. the 28a no-load quiescent current extends operating run time in batter y-powered systems. a 4.5v to 60v input supply range encompasses a wide range of system architectures and batter y chemistries. when biased from the output of the boost converter or another auxiliary supply, the ltc3769 can operate from an input supply as low as 2.3v after start-up. the operating frequency can be set within a 50khz to 900khz range or synchronized to an external clock using the internal pll. the ss pin ramps the output voltage during start-up. the pllin/mode pin selects burst mode ? operation, pulse- skipping mode or forced continuous mode at light loads. a pplica t ions 120w, 12v to 24v/5a synchronous boost converter efficiency and power loss vs output current l , lt, ltc, ltm, burst mode, opti-loop, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u. s. patents, including 5408150, 5481178, 5705919, 5929620, 6177787, 6498466, 6580258, 6611131. 3.3h 3769 ta01a boost 0.1f 4.7f tg sw bg gnd vbias v in 4.5v to 60v v out 24v/5a v out follows v in for v in > 24v ltc3769 intv cc extv cc vfb sense + sense ? ss run ith pllin/mode freq ovmode ilim pgood 22f 220f 4m 8.66k 10nf 15nf 100pf down to 2.3v after start-up if vbias is powered from v out 232k 12.1k output current (a) 0.01 0.001 0.0001 40 efficiency (%) power loss (w) 50 60 70 80 0.1 1 10 3769 ta01b 90 100 0.01 0.1 1 0.001 10 efficiency power loss ltc3769 3769f
2 for more information www.linear.com/ltc3769 a bsolu t e maxi m u m r a t ings vbias ........................................................ C0.3v to 65v boost ........................................................ C0. 3v to 71v sw ................................................................ C5v to 6 5v run ............................................................. C0. 3v to 8v maximum current sourced into pin from source >8v .............................................. 100 a pgood, pllin/mode ................................. C0. 3v to 6v intv cc , (boost - sw) .................................. C0.3v to 6v (notes 1, 3) fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 ilim intv cc freq gnd pllin/mode run ss sense ? sense + vfb pgood vbias extv cc intv cc bg boost tg sw ovmode ith 21 gnd t jmax = 150c, ja = 38c/w exposed pad (pin 21) is gnd, must be soldered to pcb 24 23 22 21 20 19 7 8 9 top view uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 vbias pgood ilim nc intv cc nc sw ovmode ith vfb sense + sense ? gnd extv cc intv cc bg boost tg freq gnd pllin/mode gnd run ss 25 gnd t jmax = 150c, ja = 47c/w exposed pad (pin 25) is gnd, must be soldered to pcb p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3769euf#pbf ltc3769euf#trpbf 3769 24-lead (4mm 4mm) plastic qfn C40c to 125c ltc3769iuf#pbf ltc3769iuf#trpbf 3769 24-lead (4mm 4mm) plastic qfn C40c to 125c ltc3769huf#pbf ltc3769huf#trpbf 3769 24-lead (4mm 4mm) plastic qfn C40c to 150c ltc3769mpuf#pbf ltc3769mpuf#trpbf 3769 24-lead (4mm 4mm) plastic qfn C55c to 150c ltc3769efe#pbf ltc3769efe#trpbf ltc3769fe 20-lead plastic ssop C40c to 125c ltc3769ife#pbf ltc3769ife#trpbf ltc3769fe 20-lead plastic ssop C40c to 125c ltc3769hfe#pbf ltc3769hfe#trpbf ltc3769fe 20-lead plastic ssop C40c to 150c ltc3769mpfe#pbf ltc3769mpfe#trpbf ltc3769fe 20-lead plastic ssop C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ extv cc ...................................................... C0.3v to 14v sense + , sense C ........................................ C0.3v to 65v (sense + - sense C ) ............................................ C0. 3v to 0.3v ilim, ss, ith, freq, phasmd, vfb ..... C0. 3v to intv cc operating junction temperature range (note 2) ........................................ C55 c to 150c storage temperature range .................. C65 c to 150c lead temperature (soldering, 10 sec) ssop ........ 300 c ltc3769 3769f 3 for more information www.linear.com/ltc3769 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c, vbias = 12v, unless otherwise noted (note 2). symbol parameter conditions min typ max units main control loop vbias chip bias voltage operating range 4.5 60 v v in sense pins common mode range (boost converter input supply voltage) 2.3 60 v v out regulated output voltage range v in 60v v v fb regulated feedback voltage i th = 1.2v (note 4) l 1.188 1.200 1.212 v feedback current (note 4) 5 50 na reference line voltage regulation vbias = 6v to 60v 0.002 0.02 %/v output voltage load regulation (note 4) measured in servo loop; i th voltage = 1.2v to 0.7v l 0.01 0.1 % measured in servo loop; i th voltage = 1.2v to 2v l C0.01 C0.1 % error amplifier transconductance i th = 1.2v 2 mmho i q input dc supply current (vbias pin) pulse-skipping or forced continuous mode sleep mode shutdown (note 5) run = 5v; v fb = 1.25v (no load) run = 5v; v fb = 1.25v (no load) run = 0v 0.9 28 4 45 10 ma a a sw pin current v sw = 12v; v boost = 16.5v; freq = 0v, forced continuous or pulse-skipping mode 700 a uvlo intv cc undervoltage lockout thresholds v intvcc ramping up v intvcc ramping down l l 3.6 4.1 3.8 4.3 v v v run run pin on threshold v run rising l 1.18 1.28 1.38 v run pin hysteresis 100 mv run pin hysteresis current v run > 1.28v 4.5 a run pin current v run < 1.28v 0.5 a soft-start charge current v ss = gnd 7 10 13 a v sense(max) maximum current sense threshold v fb = 1.1v, i lim = intv cc v fb = 1.1v, i lim = float v fb = 1.1v, i lim = gnd l l l 90 68 42 100 75 50 110 82 56 mv mv mv sense + pin current v fb = 1.1v, i lim = float 200 300 a sense C pin current v fb = 1.1v, i lim = float 1 a top gate rise time c load = 3300pf (note 6) 20 ns top gate fall time c load = 3300pf (note 6) 20 ns bottom gate rise time c load = 3300pf (note 6) 20 ns bottom gate fall time c load = 3300pf (note 6) 20 ns top gate pull-up resistance 1.2 top gate pull-down resistance 1.2 bottom gate pull-up resistance 1.2 bottom gate pull-down resistance 1.2 top gate off to bottom gate on switch-on delay time c load = 3300pf (each driver) 30 ns bottom gate off to top gate on switch-on delay time c load = 3300pf (each driver) 30 ns maximum bg duty factor 96 % t on(min) minimum bg on-time (note 7) 110 ns ltc3769 3769f 4 for more information www.linear.com/ltc3769 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c, vbias = 12v, unless otherwise noted (note 2). note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3769 is tested under pulsed load conditions such that t j t a . the ltc3769e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3769i is guaranteed over the C40c to 125c operating junction temperature range, the ltc3769h is guaranteed over the C40c to 150c operating temperature range and the ltc3769mp is tested and guaranteed over the full C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where ja = 47c/w for the qfn package and ja = 38c/w for the tssop package. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: the ltc3769 is tested in a feedback loop that servos v fb to the output of the error amplifier while maintaining i th at the midpoint of the current limit range. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: see minimum on-time considerations in the applications information section. symbol parameter conditions min typ max units intv cc linear regulator internal v cc voltage 6v < v bias < 60v, v extvcc = 0 5.2 5.4 5.6 v intv cc load regulation i cc = 0ma to 50ma 0.5 2 % internal v cc voltage 6v < v extvcc < 13v 5.2 5.4 5.6 v intv cc load regulation i cc = 0ma to 40ma, v extvcc = 8.5v 0.5 2 % extv cc switchover voltage extv cc ramping positive l 4.5 4.8 5 v extv cc hysteresis 250 mv oscillator and phase-locked loop programmable frequency r freq = 25k r freq = 60k r freq = 100k 335 105 400 760 465 khz khz khz f low lowest fixed frequency v freq = 0v 320 350 380 khz highest fixed frequency v freq = intv cc 488 535 585 khz synchronizable frequency pllin/mode = external clock l 75 850 khz pgood output pgood voltage low i pgood = 2ma 0.2 0.4 v pgood leakage current v pgood = 5v 1 a pgood trip level v fb with respect to set regulated voltage v fb ramping negative hysteresis C12 C10 2.5 C8 % % v fb ramping positive hysteresis 8 10 2.5 12 % % pgood delay pgood going high to low 45 s ov protection threshold v fb ramping positive, ovmode = 0v 1.296 1.32 1.344 v boost charge pump boost charge pump available output current v sw = 12v; v boost C v sw = 4.5v; freq = 0v, forced continuous or pulse-skipping mode 55 a ltc3769 3769f 5 for more information www.linear.com/ltc3769 typical p er f or m ance c harac t eris t ics load step burst mode operation load step forced continuous mode load step pulse-skipping mode efficiency and power loss vs output current efficiency and power loss vs output current efficiency vs input voltage inductor currents at light load soft start-up t a = 25c unless otherwise noted. output current (a) 0.01 40 efficiency (%) power loss (w) 50 60 70 80 0.1 1 10 3769 g01 30 20 10 0 90 100 0.1 0.01 0.001 0.0001 10 1 fcm efficiency fcm loss pulse-skipping efficiency pulse-skipping loss v in = 12v v out = 24v figure 8 circuit output current (a) 0.01 0.001 0.0001 40 efficiency (%) power loss (w) 50 60 70 80 0.1 1 10 3769 g02 90 100 0.01 0.1 1 0.001 10 efficiency power loss v in = 12v v out = 24v figure 8 circuit input voltage (v) 0 98 99 100 20 3769 g03 97 96 5 10 15 25 95 94 93 efficiency (%) v out = 12v v out = 24v i load = 2a figure 8 circuit v run 5v/div 0v v out 5v/div v in = 12v v out = 24v figure 8 circuit 20ms/div 3769 g08 load step 2a/div v out 500mv/div 200s/div 3769 g04 v in = 12v v out = 24v load step from 200ma to 2.5a figure 8 circuit inductor current 5a/div load step 2a/div v out 500mv/div 200s/div 3769 g05 v in = 12v v out = 24v load step from 200ma to 2.5a figure 8 circuit inductor current 5a/div load step 2a/div v out 500mv/div 200s/div 3769 g06 v in = 12v v out = 24v load step from 200ma to 2.5a figure 8 circuit inductor current 5a/div burst mode operation 5a/div pulse- skipping mode 5s/div 3769 g07 v in = 12v v out = 24v i load = 200a figure 8 circuit forced continuous mode ltc3769 3769f 6 for more information www.linear.com/ltc3769 quiescent current vs temperature intv cc line regulation shutdown (run) threshold vs temperature undervoltage lockout threshold vs temperature shutdown current vs temperature soft-start pull-up current vs temperature shutdown current vs input voltage typical p er f or m ance c harac t eris t ics t a = 25c unless otherwise noted. temperature (c) soft-start current (a) 10.5 3769 g10 9.0 11.0 10.0 9.5 ?60 15 ?35 ?10 40 65 90 140115 temperature (c) shutdown current (a) 4.5 4.0 3769 g11 1.0 1.5 2.0 3.0 3.5 6.0 5.5 5.0 2.5 ?60 15 ?35 ?10 40 65 90 140115 v in = 12v input voltage (v) shutdown current (a) 7.5 3769 g12 0 5.0 12.5 10.0 2.5 5 15 10 20 25 40 45 50 3530 6555 60 v in = 12v temperature (c) quiescent current (a) 35 3769 g13 10 30 50 45 40 25 20 15 ?60 ?35 40 65 90 15?10 115 140 v in = 12v v fb = 1.25v run = gnd ?60 15 ?35 ?10 40 65 90 140115 temperature (c) run pin voltage (v) 3769 g14 1.25 1.15 1.10 1.40 1.35 1.30 1.20 run falling run rising temperature (c) intv cc voltage (v) 3.6 4.1 4.2 4.3 4.4 3.9 3.5 4.0 3.4 3.8 3.7 3769 g15 ?60 15 ?35 ?10 40 65 90 140115 intv cc rising intv cc falling input voltage (v) intv cc voltage (v) 5.2 3769 g16 4.5 5.1 5.5 5.4 5.3 5.0 4.9 4.8 4.7 4.6 0 5 10 45 50 55 30 35 40 15 20 25 60 65 regulated feedback voltage vs temperature temperature (c) ?60 regulated feedback voltage (v) 1.209 15 3769 g09 1.200 1.194 ?35 ?10 40 1.191 1.188 1.212 1.206 1.203 1.197 65 90 140115 ltc3769 3769f 7 for more information www.linear.com/ltc3769 extv cc switchover and intv cc voltages vs temperature intv cc vs intv cc load current sense pin input current vs temperature oscillator frequency vs temperature maximum current sense threshold vs i th voltage sense pin input current vs v sense voltage sense pin input current vs i th voltage oscillator frequency vs input voltage typical p er f or m ance c harac t eris t ics t a = 25c unless otherwise noted. intv cc load current (ma) 0 intv cc voltage (v) 5.35 5.40 5.45 140 5.30 5.25 40 80 20 180 60 100 160 120 200 5.20 5.00 5.10 5.05 5.15 5.50 3769 g17 extv cc = 0v extv cc = 6v v in = 12v temperature (c) 4.0 extv cc and intv cc voltage (v) 4.2 4.6 4.8 5.0 6.0 5.4 4.4 5.6 5.8 5.2 3769 g18 ?60 15 ?35 ?10 40 65 90 140115 intv cc extv cc rising extv cc falling temperature (c) 300 frequency (khz) 350 600 450 500 550 400 3769 g19 ?60 15 ?35 ?10 40 65 90 140115 freq = intv cc freq = gnd 15 5 10 20 25 30 35 40 45 50 55 60 65 input voltage (v) oscillator frequency (khz) 344 354 356 358 360 350 342 352 340 348 346 3769 g20 freq = gnd i th voltage (v) 0 maximum current sense voltage (mv) 80 120 100 0.6 1.0 3769 g21 40 0 0.2 0.4 0.8 1.2 1.4 ?40 60 20 ?20 ?60 i lim = gnd i lim = float i lim = intv cc burst mode operation pulse-skipping mode forced continuous mode temperature (c) sense current (a) 0 80 40 160 200 240 120 20 100 60 180 220 260 140 3769 g22 ?60 15 ?35 ?10 40 65 90 140115 sense ? pin sense + pin v sense = 12v i lim = float i th voltage (v) 0 sense current (a) 1 2 2.5 0 80 40 160 200 240 120 20 100 60 180 220 260 140 0.5 1.5 3 3769 g23 sense + pin sense ? pin v sense = 12v i lim = intv cc i lim = float i lim = gnd i lim = intv cc i lim = float i lim = gnd v sense common mode voltage (v) sense current (a) 200 3769 g24 0 180 160 140 260 240 220 120 100 80 60 40 20 5 10 45 50 55 30 35 40 15 20 25 60 65 sense + pin i lim = intv cc i lim = float i lim = gnd i lim = intv cc i lim = float i lim = gnd sense ? pin ltc3769 3769f 8 for more information www.linear.com/ltc3769 p in func t ions vbias (pin 1/pin 19): main supply pin. it is normally tied to the input supply v in or to the output of the boost converter. a bypass capacitor should be tied between this pin and the signal ground pin. the operating voltage range on this pin is 4.5v to 60v (65v abs max). pgood (pin 2/pin 20): power good indicator. open-drain logic output that is pulled to ground when the output volt - age is more than 10% away from the regulated output voltage. to avoid false trips the output voltage must be outside the range for 45s before this output is activated. ilim (pin 3/pin 1): current comparator sense voltage range input. this pin is used to set the peak current sense voltage in the current comparator . connect this pin to sgnd, leave floating or connect to intv cc to set the peak current sense voltage to 50mv, 75mv or 100mv, respectively. intv cc (pins 5, 22/pins 2, 17): output of internal 5.4v ldo. power supply for control circuits and gate drivers. de- couple pin 22/17 to gnd with a minimum 4.7f low esr ceramic capacitor. connect pin 5/2 to pin 22/17 with a trace on the printed circuit board. freq (pin 7/pin 3): frequency control pin for the internal vco. connecting the pin to gnd for ces the vco to a fixed low frequency of 350khz. connecting the pin to intv cc forces the vco to a fixed high frequency of 535khz. the frequency can be programmed from 50khz to 900khz by connecting a resistor from the freq pin to gnd. the resistor and an internal 20a source current create a volt - age used by the internal oscillator to set the frequency. alternatively, this pin can be driven with a dc voltage to vary the frequency of the internal oscillator . gnd (pin 8, 10, 24, exposed pad pin 25/ pin 4, exposed pad pin 21): ground. all ground pins must be connected and the exposed pad must be soldered to the pcb for rated electrical and thermal performance. pllin/mode (pin 9/pin 5): external synchronization input to phase detector and forced continuous mode input. when an external clock is applied to this pin, the phase-locked loop will force the rising edge of bg to be synchronized with the rising edge of the external clock. when an external clock is applied to this pin, the ovmode pin is used to determine how the ltc3769 operates at light load. when not synchronizing to an external clock, this (qfn/tssop) typical p er f or m ance c harac t eris t ics t a = 25c unless otherwise noted. maximum current sense threshold vs duty cycle charge pump charging current vs operating frequency charge pump charging current vs switch voltage duty cycle (%) 0 maximum current sense voltage (mv) 80 100 70 60 40 20 40 10 90 30 50 80 60 100 20 0 120 3769 g25 i lim = intv cc i lim = float i lim = gnd operating frequency (khz) 50 0 charge pump charging current (a) 20 30 80 50 250 450 550 10 60 70 40 150 350 650 750 3769 g26 t = 130c t = 155c t = 25c t = ? 45c t = ? 60c switch voltage (v) charge pump charging current (a) 3769 g27 0 50 40 70 60 30 20 10 5 45 55 35 15 25 65 freq = gnd freq = intv cc ltc3769 3769f 9 for more information www.linear.com/ltc3769 p in func t ions (qfn/tssop) input determines how the ltc3769 operates at light loads. pulling this pin to ground selects burst mode operation. an internal 100k resistor to ground also invokes burst mode operation when the pin is floated. tying this pin to intv cc forces continuous inductor current operation. tying this pin to a voltage greater than 1.2v and less than intv cc C 1.3v selects pulse-skipping operation. this can be done by adding a 100k resistor between the pllin/ mode pin and intv cc . run (pin 11/pin 6): run control input. forcing this pin below 1.28v shuts down the controller. forcing this pin below 0.7v shuts down the entire ltc3769, reducing quiescent current to approximately 4a. an external resistor divider connected to v in can set the threshold for converter operation. once running, a 4.5a current is sourced from the run pin allowing the user to program hysteresis using the resistor values. ss (pin 12/pin 7): output soft-start input. a capacitor to ground at this pin sets the ramp rate of the output voltage during start-up. sense + (pin 13/pin 9): positive current sense comparator input. the (+) input to the current comparator is normally connected to the positive terminal of a current sense resis - tor. the current sense resistor is normally placed at the input of the boost controller in series with the inductor. this pin also supplies power to the current comparator. the common mode voltage range on sense + and sense C pins is 2.3v to 60v (65v abs max). sense C (pin 14/pin 8): negative current sense comparator input. the (C) input to the current comparator is normally connected to the negative terminal of a current sense resistor connected in series with the inductor. vfb (pin 15/pin 10): error amplifier feedback input. this pin receives the remotely sensed feedback voltage from an external resistive divider connected across the output. ith (pin 16/pin 11): current control threshold and error amplifier compensation point. the voltage on this pin sets the current trip threshold. ovmode (pin 17/pin 12): overvoltage mode selection input. this pin is used to select how the ltc3769 operates when the output feedback voltage (v fb ) is overvoltage (>110% of its normal regulated point of 1.2v). it is also used to determine the light-load mode of operation when the ltc3769 is synchronized to an external clock through the pllin/mode pin. when ovmode is tied to ground, overvoltage protection is enabled and the top mosfet gate (tg) is turned on continuously until the overvoltage condition is cleared. when ovmode is grounded, the ltc3769 operates in forced continuous mode when synchronized. there is an internal weak pull-down resistor that pulls the ovmode pin to ground when it is left floating. when ovmode is tied to intv cc , overvoltage protection is disabled and tg is not forced on during an overvolt - age event. instead, the state of tg is determined by the mode of operation selected by the pllin/mode pin and the inductor current. see the operation section for more details. when ovmode is tied to int v cc , the ltc3769 operates in pulse-skipping mode when synchronized. sw (pin 18/pin 13): switch node. connect to the source of the synchronous n-channel mosfet, the drain of the main n-channel mosfet and the inductor. tg (pin 19/pin 14): top gate. connect to the gate of the synchronous n-channel mosfet. boost (pin 20/pin 15): floating power supply for the synchronous n-channel mosfet. bypass to sw with a capacitor and supply with a schottky diode connected to intv cc . bg (pin 21/pin 16): bottom gate. connect to the gate of the main n-channel mosfet. extv cc (pin 23/pin 18): external power input to an internal ldo connected to intv cc . this ldo supplies intv cc power, bypassing the internal ldo powered from v bias whenever extv cc is higher than 4.7v. see extv cc connection in the applications information section. do not float or exceed 14v on this pin. connect to ground if not used. ltc3769 3769f 10 for more information www.linear.com/ltc3769 b lock diagra m sleep switching logic and charge pump + ? 4.8v 3.8v vbias v in c in intv cc pllin/ mode pgood + ? 1.32v 1.08v ? + + ? + ? + vfb extv cc 5.4v ldo vco pfd sw 0.425v sens lo boost tg c b c out v out d b pgnd bg intv cc vfb s r q ea 1.32v ss 1.2v r sense 0.5a/ 4.5a 10a 11v shdn ? + shdn 2.3v ? + r c ss sens lo ith c c c ss c c2 0.7v 2.8v slope comp 2mv + ? ? + sense ? sense + shdn clk run sgnd intv cc ovmode freq + ? + ? l + ? en 5.4v ldo en 20a 100k 5m sync det ilim ov 3769 bd current limit i cmp i rev ltc3769 3769f 11 for more information www.linear.com/ltc3769 o pera t ion main control loop the ltc3769 uses a constant-frequency, current mode step-up architecture. during normal operation, each external bottom mosfet is turned on when the clock for that channel sets the rs latch, and is turned off when the main current comparator, icmp, resets the rs latch. the peak inductor current at which icmp trips and resets the latch is controlled by the voltage on the ith pin, which is the output of the error amplifier ea. the error amplifier compares the output voltage feedback signal at the vfb pin (which is generated with an external resistor divider connected across the output voltage, v out , to ground), to the internal 1.200v reference voltage. in a boost converter, the required inductor current is determined by the load current, v in and v out . when the load current increases, it causes a slight decrease in vfb relative to the reference, which causes the ea to increase the ith voltage until the average inductor current in each channel matches the new requirement based on the new load current. after the bottom mosfet is turned off each cycle, the top mosfet is turned on until either the inductor current starts to reverse, as indicated by the current comparator, i rev , or the beginning of the next clock cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is tied to a voltage less than 4.8v, the vbias ldo (low dropout linear regulator) supplies 5.4v from vbias to intv cc . if extv cc is taken above 4.8v, the vbias ldo is turned off and an extv cc ldo is turned on. once enabled, the extv cc ldo supplies 5.4v from extv cc to intv cc . using the extv cc pin allows the intv cc power to be derived from an external source, thus removing the power dissipation of the vbias ldo. shutdown and start-up (run and ss pins) the ltc3769 can be shut down using the run pin. pulling this pin below 1.28v shuts down the main control loops. pulling this pin below 0.7v disables the controller and most internal circuits, including the intv cc ldos. in this state, the ltc3769 draws only 4a of quiescent current. note: do not apply a heavy load to the boost converter for an extended time while the ltc3769 is in shutdown. the top mosfet is turned off during shutdown and the output load may cause excessive dissipation in the body diode. the run pin may be externally pulled up or driven directly by logic. when driving the run pin with a low impedance source, do not exceed the absolute maximum rating of 8v. the run pin has an internal 11v voltage clamp that allows the run pin to be connected through a resistor to a higher voltage (for example, v in ), as long as the maxi- mum current into the run pin does not exceed 100a. an external resistor divider connected to v in can set the threshold for converter operation. once running, a 4.5a current is sourced from the run pin allowing the user to program hysteresis using the resistor values. the start-up of the controllers output voltage v out is controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the 1.2v internal reference, the ltc3769 regulates the vfb voltage to the ss pin voltage instead of the 1.2v reference. this allows the ss pin to be used to program a soft-start by connecting an external capacitor from the ss pin to sgnd. an internal 10a pull - up current charges this capacitor creating a voltage ramp on the ss pin. as the ss voltage rises linearly from 0v to 1.2v (and beyond up to intv cc ), the output voltage rises smoothly to its final value. light load current operationburst mode operation, pulse-skipping or continuous conduction (pllin/mode pin) the ltc3769 can be enabled to enter high efficiency burst mode operation, constant-frequency, pulse-skipping mode or forced continuous conduction mode at low load currents. to select burst mode operation, tie the pllin/mode pin to ground (e.g., sgnd). to select forced continuous operation, tie the pllin/mode pin to intv cc . to select pulse-skipping mode, tie the pllin/ mode pin to a dc voltage greater than 1.2v and less than intv cc C 1.3v. when the controller is enabled for burst mode opera- tion, the minimum peak current in the inductor is set to ltc3769 3769f 12 for more information www.linear.com/ltc3769 approximately 30% of the maximum sense voltage even though the voltage on the ith pin indicates a lower value. if the average inductor current is higher than the required current, the error amplifier ea will decrease the voltage on the ith pin. when the ith voltage drops below 0.425v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. in sleep mode much of the internal circuitry is turned off and the ltc3769 draws only 28a of quiescent current. in sleep mode the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the sleep signal goes low and the controller resumes normal operation by turning on the bottom external mosfet on the next cycle of the internal oscillator. when the controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (i rev ) turns off the top external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates in discontinuous current operation. in forced continuous operation or when clocked by an e xternal clock source to use the phase-locked loop (see the frequency selection and phase-locked loop section), the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor cur - rent is determined by the voltage on the ith pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continuous operation has the advantages of lower output voltage ripple and less interference to audio cir cuitr y, as it maintains constant-frequency operation independent of load current. when the pllin/mode pin is connected for pulse-skipping mode, the ltc3769 operates in pwm pulse-skipping mode at light loads. in this mode, constant-frequency operation is maintained down to approximately 1% of designed maximum output current. at very light loads, the current comparator icmp may remain tripped for several cycles and force the external bottom mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq and pllin/mode pins) the selection of switching frequency is a trade-off between efficiency and component size. low frequency opera- tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the ltc3769 s controllers can be selected using the freq pin. if the pllin/mode pin is not being driven by an external clock source, the freq pin can be tied to sgnd, tied to in tv cc , or programmed through an external resistor. tying freq to sgnd selects 350khz while tying freq to intv cc selects 535khz. placing a resistor between freq and sgnd allows the frequency to be programmed between 50khz and 900khz, as shown in figure 7. a phase-locked loop (pll) is available on the ltc3769 to synchronize the internal oscillator to an external clock source that is connected to the pllin/mode pin. the ltc3769s phase detector adjusts the voltage (through an internal lowpass filter) of the vco input so that the turn-on of the external bottom mosfet is 180 out-of-phase to the rising edge of the external clock source. when syn - chronized, the ltc3769 will operate in forced continuous mode of operation if the ovmode pin is grounded. if the ovmode pin is tied to intv cc , the ltc3769 will operate in pulse-skipping mode of operation when synchronized. the vco input voltage is prebiased to the operating fre - quency set by the freq pin before the external clock is applied. if prebiased near the external clock frequency, the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clocks to the rising edge of bg1. the ability to prebias the loop filter allows the pll to lock-in rapidly without deviating far from the desired frequency. o pera t ion ltc3769 3769f 13 for more information www.linear.com/ltc3769 o pera t ion the typical capture range of the ltc3769s pll is from approximately 55khz to 1mhz, and is guaranteed to lock to an external clock source whose frequency is between 75khz and 850khz. the typical input clock thresholds on the pllin/mode pin are 1.6v (rising) and 1.2v (falling). the recommended maximum amplitude for low level and minimum amplitude for high level of external clock are 0v and 2.5v, respectively. operation when v in > regulated v out when v in rises above the regulated v out voltage, the boost controller can behave differently depending on the mode, inductor current and v in voltage. in forced continuous mode, the control loop works to keep the top mosfet on continuously once v in rises above v out . the internal charge pump delivers current to the boost capacitor to maintain a sufficiently high tg voltage. the amount of current the charge pump can deliver is characterized by two curves in the typical performance characteristics section. in pulse-skipping mode, if v in is between 100% and 110% of the regulated v out voltage, tg turns on if the inductor current rises above a certain threshold and turns off if the inductor current falls below this threshold. this threshold current is set to approximately 6%, 4% or 3% of the maximum ilim current when the ilim pin is grounded, floating or tied to intv cc , respectively. if the controller is programmed to burst mode operation under this same v in window, then tg remains off regardless of the inductor current. if the ovmode pin is grounded and v in rises above 110% of the regulated v out voltage in any mode, the controller turns on tg regardless of the inductor current. in burst mode operation, however, the internal charge pump turns off if the chip is asleep. with the charge pump off, there would be nothing to prevent the boost capacitor from discharging, resulting in an insufficient tg voltage needed to keep the top mosfet completely on. to prevent exces - sive power dissipation across the body diode of the top mosfet in this situation, the chip can be switched over to forced continuous mode to enable the charge pump; a schottky diode can also be placed in parallel with the top mosfet. power good the pgood pin is connected to an open drain of an internal n-channel mosfet . the mosfet turns on and pulls the pgood pin low when the vfb pin voltage is not within 10% of the 1.2v reference voltage. the pgood pin is also pulled low when the corresponding run pin is low (shut down). when the vfb pin voltage is within the 10% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6v (abs max). overvoltage mode selection the ovmode pin is used to select how the ltc3769 operates during an overvoltage event, defined as when the output feedback voltage (v fb ) is greater than 110% of its normal regulated point of 1.2v. it is also used to determine the light-load mode of operation when the ltc3769 is synchronized to an external clock through the pllin/mode pin. the ovmode pin is a logic input that should normally be tied to intv cc or grounded. alternatively, the pin can be left floating, which allow a weak internal resistor to pull it down to ground. ovmode = intv cc : an overvoltage event causes the error amplifier to pull the ith pin low. in burst mode operation, this causes the ltc3769 to go to sleep and tg and bg are held off. in pulse-skipping mode, bg is held off and tg will turn on if the inductor current is positive. in forced continuous mode, tg (and bg) will switch on and off as the ltc3769 will regulate the inductor current to a negative peak value (corresponding to ith = 0v) to discharge the output. when ovmode is tied to intv cc , the ltc3769 operates in pulse-skipping mode when synchronized. in summary, with ovmode = intv cc , the inductor cur - rent is not allowed to go negative (reverse from output to input) except in forced continuous mode, where it does reverse current but in a controlled manner with a regulated negative peak current. ovmode should be tied to intv cc in applications where the output voltage may sometimes be above its regulation point (for example, if the output ltc3769 3769f 14 for more information www.linear.com/ltc3769 o pera t ion is a battery or if there are other power supplies driving the output) and no reverse current flow from output to input is desired. ovmode grounded or left floating: when ovmode is grounded or left floating, overvoltage protection is enabled and tg is turned on continuously until the overvoltage condition is cleared, regardless of whether burst mode operation, pulse-skipping mode, or forced continuous mode is selected by the pllin/mode pin. this can cause large negative inductor currents to flow from the output to the input if the output voltage is higher than the input voltage. note however that in burst mode operation, the ltc3769 is in sleep during an overvoltage condition, which disables the internal oscillator and boost-sw charge pump. so the boost-sw voltage may discharge (due to leakage) if the overvoltage conditions persists indefinitely. if boost-sw discharges, then by definition tg would turn off. when ovmode is grounded or left floating, the ltc3769 operates in forced continuous mode when synchronized. ovmode should be tied to ground or left floating in cir - cuits, such as automotive applications, where the input voltage can often be above the regulated output voltage and it is desirable to turn on tg to pass through the input voltage to the output. operation at low sense pin common mode voltage the current comparator in the ltc3769 is powered directly from the sense + pin. this enables the common mode voltage of the sense + and sense C pins to operate at as low as 2.3v, which is below the uvlo threshold. figure 10 shows a typical application in which the controllers vbias is powered from v out while the v in supply can go as low as 2.3v. if the voltage on sense + drops below 2.3v, the ss pin will be held low. when the sense voltage returns to the normal operating range, the ss pin will be released, initiating a new soft-start cycle. boost supply refresh and internal charge pump the top mosfet driver is biased from the floating bootstrap capacitor, c b , which normally recharges during each cycle through an external diode when the bottom mosfet turns on. there are two considerations for keeping the boost supply at the required bias level. during start-up, if the bottom mosfet is not turned on within 200s after uvlo goes low, the bottom mosfet will be forced to turn on for ~400ns. this forced refresh generates enough boost-sw voltage to allow the top mosfet ready to be fully enhanced instead of waiting for the initial few cycles to charge up. there is also an internal charge pump that keeps the required bias on boost. the charge pump always operates in both forced continuous mode and pulse-skipping mode. in burst mode operation, the charge pump is turned off during sleep and enabled when the chip wakes up. the internal charge pump can normally supply a charging current of 55a. ltc3769 3769f 15 for more information www.linear.com/ltc3769 the typical application on the first page is a basic ltc3769 application circuit. the ltc3769 can be configured to use either inductor dcr (dc resistance) sensing or a discrete sense resistor (r sense ) for current sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it does not require current sensing resistors and is more power-efficient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets are selected. finally, input and output capacitors are selected. sense + and sense C pins the sense + and sense C pins are the inputs to the cur - rent comparators. the common mode input voltage range of the current comparators is 2.3v to 60v. the current sense resistor is normally placed at the input of the boost controller in series with the inductor. a pplica t ions i n f or m a t ion the sense + pin also provides power to the current com - parator. it draws ~200a during normal operation. there is a small base current of less than 1a that flows into the sense C pin. the high impedance sense C input to the current comparators allows accurate dcr sensing. filter components mutual to the sense lines should be placed close to the ltc3769, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 1). sensing cur - rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if dcr sensing is used (figure 2b), resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. figure 1. sense lines placement with inductor or sense resistor (2a) using a resistor to sense current (2b) using the inductor dcr to sense current figure 2. two different methods of sensing current v in to sense filter, next to the controller inductor or r sense 3769 f01 tg sw bg ltc3769 intv cc boost sense + sense ? (optional) vbias v in v out gnd 3769 f02a tg sw bg inductor dcr l ltc3769 intv cc boost sense + sense ? r2c1 r1 vbias v in v out place c1 near sense pins gnd 3769 f02b (r1 || r2) ? c1 = l dcr r sense(eq) = dcr ? r2 r1 + r2 ltc3769 3769f 16 for more information www.linear.com/ltc3769 a pplica t ions i n f or m a t ion sense resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) . when the ilim pin is grounded, floating or tied to intv cc , the maximum threshold is set to 50mv, 75mv or 100mv, respectively. the current comparator threshold sets the peak of the inductor current, yielding a maximum average inductor current, i max , equal to the peak value less half the peak-to-peak ripple current, i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + i l 2 the actual value of i max depends on the required output current i out(max) and can be calculated using: i max = i out(max) ? v out v in when using the controller in low v in and very high voltage output applications, the maximum inductor current and correspondingly the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for boost regulators operating at greater than 50% duty factor. a curve is provided in the typical performance characteristics section to estimate this reduction in peak inductor current level depending upon the operating duty factor. inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the ltc3769 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 2b. the dcr of the inductor can be less than 1m for high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor could reduce the efficiency by a few percent compared to dcr sensing. *guiffufsobm33tujnfdpotuboujtdiptfoupcf exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature. consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the induct- or value calculation section, the target sense resistor value is: r sense(equiv) = v sense(max) i max + i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ). next, determine the dcr of the inductor. where provided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/c. a conservative value for the maximum inductor temperature (t l(max) ) is 100c. to scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r d = r sense(equiv) dcr max at t l(max) c1 is usually selected to be in the range of 0.1f to 0.47f. this forces r1|| r2 to around 2k, reducing error that might have been caused by the sense C pins 1a current. the equivalent resistance r1|| r2 is scaled to the room temperature inductance and maximum dcr: r1||r2 = l (dcr at 20 c) ? c1 ltc3769 3769f 17 for more information www.linear.com/ltc3769 a pplica t ions i n f or m a t ion the sense resistor values are: r1 = r1||r2 r d ; r2 = r1 ? r d 1 ? r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at v in = 1/2v out : p loss_r1 = (v out ? v in ) ? v in r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduc - tion losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. inductor value calculation the operating frequency and inductor selection are in - terrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet gate charge and switching losses. also, at higher frequency the duty cycle of body diode conduction is higher, which results in lower efficiency. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current i l decreases with higher inductance or frequency and increases with higher v in : i l = v in f ? l 1 ? v in v out ? ? ? ? ? ? accepting larger values of i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is i l = 0.3(i max ). the maximum i l occurs at v in = 1/2v out . the inductor value also has secondary effects. the tran - sition to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. once the value of l is known, an inductor with low dcr and low core losses should be selected. power mosfet selection two external power mosfets must be selected for the ltc3769: one n-channel mosfet for the bottom (main) switch, and one n-channel mosfet for the top (synchro - nous) switch. the peak-to-peak gate drive levels are set by the int v cc voltage. this voltage is typically 5.4v during start-up (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. pay close attention to the bv dss specification for the mosfets as well; many of the logic level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance r ds(on) , miller capacitance c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in vds. this result is then multiplied by the ratio of the application applied vds to the gate charge curve specified vds. when the ic is operating in continuous mode, the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out ? v in v out synchronous switch duty cycle = v in v out ltc3769 3769f 18 for more information www.linear.com/ltc3769 a pplica t ions i n f or m a t ion if the maximum output current is i out(max) the mosfet power dissipation at maximum output current is given by: p main = (v out v in )v out v 2 in ? i out(max) 2 ? 1 + ( ) ? r ds(on) + k ? v out 3 ? i out(max) v in ? ? c miller ? f p sync = v in v out i out(max) 2 ? 1 + ( ) ? r ds(on) where d is the temperature dependency of r ds(on) . the constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7. both mosfets have i 2 r losses while the bottom n-channel equation includes an additional term for transition losses, which are highest at low input voltages. for high v in the high current efficiency generally improves with larger mosfets, while for low v in the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the bottom switch duty factor is low or dur - ing overvoltage when the synchronous switch is on close to 100% of the period. the term (1+ d) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/c can be used as an approximation for low voltage mosfets. c in and c out selection the input ripple current in a boost converter is relatively low (compared with the output ripple current), because this current is continuous. the input capacitor c in voltage rating should comfortably exceed the maximum input voltage. although ceramic capacitors can be relatively tolerant of overvoltage conditions, aluminum electrolytic capacitors are not. be sure to characterize the input voltage for any possible overvoltage transients that could apply excess stress to the input capacitors. the value of c in is a function of the source impedance, and in general, the higher the source impedance, the higher the required input capacitance. the required amount of input capacitance is also greatly affected by the duty cycle. high output current applications that also experience high duty cycles can place great demands on the input supply, both in terms of dc current and ripple current. in a boost converter, the output has a discontinuous current, so c out must be capable of reducing the output voltage ripple. the effects of esr (equivalent series resistance) and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. the steady ripple voltage due to charging and discharging the bulk capacitance in a single phase boost converter is given by: v ripple = i out(max) ? (v out ? v in(min) ) c out ? v out ? f v where c out is the output filter capacitor. the steady ripple due to the voltage drop across the esr is given by: v esr = i l(max) ? esr multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient. capacitors are now available with low esr and high ripple current ratings (e.g., os-con and poscap). ltc3769 3769f 19 for more information www.linear.com/ltc3769 a pplica t ions i n f or m a t ion setting output voltage the ltc3769 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in figure 3. the regulated output voltage is determined by: v out = 1.2v 1 + r b r a ? ? ? ? ? ? great care should be taken to route the vfb line away from noise sources, such as the inductor or the sw line. also place the feedback resistor divider close to the vfb pin and keep the vfb node as small as possible to avoid noise pickup. intv cc regulators the ltc3769 features two separate internal p-channel low dropout linear regulators (ldo) that supply power at the intv cc pin from either the vbias supply pin or the extv cc pin depending on the connection of the extv cc pin. intv cc powers the gate drivers and much of the ltc3769s internal circuitry. the vbias ldo and the extv cc ldo regulate intv cc to 5.4v. each of these can supply at least 50ma and must be bypassed to ground with a minimum of a 4.7f ceramic capacitor. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi - mum junction temperature rating for the ltc3769 to be exceeded. the int v cc current, which is dominated by the gate charge current, may be supplied by either the vbias ldo or the extv cc ldo. when the voltage on the extv cc pin is less than 4.8v, the vbias ldo is enabled. in this case, power dissipation for the ic is highest and is equal to vbias ? i intvcc . the gate charge current is dependent on operating frequency, as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics. for example, at 70c ambient temperature, the ltc3769 intv cc current is limited to less than 19ma in the qfn package from a 60v vbias supply when not using the extv cc supply: t j = 70c + (19ma)(60v)(47c/w) = 125c soft-start (ss pin) the start-up of v out is controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the internal 1.2v reference, the ltc3769 regulates the vfb pin voltage to the voltage on the ss pin instead of 1.2v. soft-start is enabled by simply connecting a capacitor from the ss pin to ground, as shown in figure 4. an internal 10a current source charges the capacitor, providing a linear ramping voltage at the ss pin. the ltc3769 will regulate the vfb pin (and hence, v out ) according to the voltage on the ss pin, allowing v out to rise smoothly from v in to its final regulated value. the total soft-start time will be approximately: t ss = c ss ? 1.2v 10a figure 4. using the ss pin to program soft-start figure 3. setting output voltage ltc3769 vfb v out r b r a 3769 f03 ltc3769 ss c ss gnd 3769 f04 ltc3769 3769f 20 for more information www.linear.com/ltc3769 a pplica t ions i n f or m a t ion in the tssop package, the intv cc current is limited to less than 24ma from a 60v supply when not using the extv cc supply: t j = 70c + (24ma)(60v)(38c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (pllin/mode = intv cc ) at maximum v in . when the voltage applied to extv cc rises above 4.8v, the v in ldo is turned off and the extv cc ldo is enabled. the extv cc ldo remains on as long as the voltage applied to extv cc remains above 4.55v. the extv cc ldo attempts to regulate the intv cc voltage to 5.4v, so while extv cc is less than 5.4v, the ldo is in dropout and the intv cc voltage is approximately equal to extv cc . when extv cc is greater than 5.4v, up to an absolute maximum of 14v, intv cc is regulated to 5.4v. significant thermal gains can be realized by powering intv cc from an external supply. tying the extv cc pin to a 5v supply reduces the junction temperature in the previous example from 125c to 75c in a qfn package: t j = 70c + (19ma)(5v)(47c/w) = 75c and from 125c to 75c in the tssop package: t j = 70c + (24ma)(5v)(38c/w) = 75c the following list summarizes possible connections for extv cc : extv cc grounded. this will cause intv cc to be powered from the internal 5.4v regulator resulting in an efficiency penalty at high v bias voltages. extv cc connected to an external supply. if an external supply is available in the 5v to 14v range, it may be used to provide power. ensure that extv cc is always lower than or equal to vbias. topside mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet. capacitor c b in the block diagram is charged though external diode d b from intv cc when the sw pin is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate and source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v out and the boost pin follows. with the topside mosfet on, the boost voltage is above the output voltage: v boost = v out + v intvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external diode d b must be greater than v out(max) . the external diode d b can be a schottky diode or silicon diode, but in either case it should have low leakage and fast recovery. pay close attention to the reverse leakage at high temperatures, where it generally increases substantially. the topside mosfet driver includes an internal charge pump that delivers current to the bootstrap capacitor from the boost pin. this charge current maintains the bias voltage required to keep the top mosfet on continuously during dropout/overvoltage conditions. the schottky/ silicon diode selected for the topside driver should have a reverse leakage less than the available output current the charge pump can supply. curves displaying the available charge pump current under different operating conditions can be found in the typical performance characteristics section. a leaky diode d b in the boost converter can not only prevent the top mosfet from fully turning on but it can also completely discharge the bootstrap capacitor c b and create a current path from the input voltage to the boost pin to intv cc . this can cause intv cc to rise if the diode leakage exceeds the current consumption on intv cc . this is particularly a concern in burst mode operation ltc3769 3769f 21 for more information www.linear.com/ltc3769 a pplica t ions i n f or m a t ion an amount of time corresponding to the phase difference. the voltage at the vco input is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the internal filter capacitor, c lp , holds the voltage at the vco input. where the load on intv cc can be very small. the external schottky or silicon diode should be carefully chosen such that intv cc never gets charged up much higher than its normal regulation voltage. fault conditions: overtemperature protection at higher temperatures, or in cases where the internal power dissipation causes excessive self heating on-chip (such as an intv cc short to ground), the overtemperature shutdown circuitry will shut down the ltc3769. when the junction temperature exceeds approximately 170c, the overtemperature circuitry disables the intv cc ldo, causing the intv cc supply to collapse and effectively shut down the entire ltc3769 chip. once the junction temperature drops back to approximately 155c, the intv cc ldo turns back on. long term overstress (t j > 125c) should be avoided as it can degrade the performance or shorten the life of the part. since the shutdown may occur at full load, beware that the load current will result in high power dissipation in the body diodes of the top mosfets. in this case, the pgood output may be used to turn the system load off. phase-locked loop and frequency synchronization the ltc3769 has an internal phase-locked loop (pll) comprised of a phase frequency detector, a lowpass filter and a voltage-controlled oscillator (vco). this allows the turn-on of the bottom mosfet to be locked signal applied to 180 degrees out-of-phase to the rising edge of the external clock. the phase detector is an edge-sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sourced continu - ously from the phase detector output, pulling up the vco input. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the vco input. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for figure 5. relationship between oscillator frequency and resistor value at the freq pin freq pin resistor (k ) 15 frequency (khz) 600 800 1000 35 45 55 25 3769 f05 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125 typically, the external clock (on the pllin/mode pin) input high threshold is 1.6v, while the input low threshold is 1.2v. note that the ltc3769 can only be synchronized to an external clock whose frequency is within range of the ltc3769s internal vco, which is nominally 55khz to 1mhz. this is guaranteed to be between 75khz and 850khz. rapid phase locking can be achieved by using the freq pin to set a free-running frequency near the desired synchro - nization frequency. the vcos input voltage is prebiased at a frequency corresponding to the frequency set by the freq pin. once prebiased, the pll only needs to adjust the frequency slightly to achieve phase lock and synchro - nization. although it is not required that the free-running frequency be near external clock frequency , doing so will prevent the operating frequency from passing through a large range of frequencies as the pll locks. ltc3769 3769f 22 for more information www.linear.com/ltc3769 a pplica t ions i n f or m a t ion table 1 summarizes the different states in which the freq pin can be used. table 1. freq pin pllin/mode pin frequency 0v dc voltage 350khz intv cc dc voltage 535khz resistor dc voltage 50khz to 900khz any of the above external clock phase locked to external clock minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the ltc3769 is capable of turning on the bottom mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on- time limit. in forced continuous mode, if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles but the output will continue to be regulated. more cycles will be skipped when v in increases. once v in rises above v out , the loop keeps the top mosfet continuously on. the minimum on-time for the ltc3769 is approximately 110ns. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the greatest improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc., are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, five main sources usually account for most of the losses in ltc3769 circuits: 1) ic vbias current, 2) intv cc regulator current, 3) i 2 r losses, 4) bottom mosfet transi - tion losses, 5) body diode conduction losses. 1. the vbias current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. vbias current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. 3. dc i 2 r losses. these arise from the resistances of the mosfets, sensing resistor, inductor and pc board traces and cause the efficiency to drop at high output currents. 4. transition losses apply only to the bottom mosfet(s), and become significant only when operating at low input voltages. transition losses can be estimated from: transition loss = (1.7) v out 3 v in ? i out(max) ? c rss ? f 5. body diode conduction losses are more significant at higher switching frequency. during the dead time, the loss in the top mosfet is i out ? v ds , where v ds is around 0.7v. at higher switching frequency, the dead time becomes a good percentage of switching cycle and causes the ef - ficiency to drop. ltc3769 3769f 23 for more information www.linear.com/ltc3769 a pplica t ions i n f or m a t ion other hidden losses, such as copper trace and internal battery resistances, can account for an additional efficiency degradation in portable systems. it is very important to include these system-level losses during the design phase. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or discharge c out , generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive over - shoot or ringing, which would indicate a stability problem. opti-loop ? compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the ith pin not only allows optimization of control loop behavior, but it also provides a dc coupled and ac filtered closed loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/ or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the ith external components shown in the figure 10 circuit will provide an adequate starting point for most applications. the ith series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly to optimize transient response once the final pc layout is complete and the particular output capacitor type and value have been determined. the output capacitors must be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet and load resistor directly across the output capacitor and driving the gate with an ap - propriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by de - creasing c c . if rc is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus, a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. design example as a design example, assume v in = 12v (nominal), v in = 22v (max), v out = 24v, i out(max) = 4a, v sense(max) = 75mv, and f = 350khz. the inductance value is chosen first based on a 30% ripple current assumption. tie the freq pin to gnd, generat - ltc3769 3769f 24 for more information www.linear.com/ltc3769 a pplica t ions i n f or m a t ion ing 350khz operation. the minimum inductance for 30% ripple current is: i l = v in f ? l 1 ? v in v out ? ? ? ? ? ? the largest ripple happens when v in = 1/2v out = 12v, where the average maximum inductor current is: i max = i out(max) ? v out v in = 8a a 6.8h inductor will produce a 31% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 9.25a. the r sense resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances: r sense 75mv 9.25a = 0.008 choosing 1% resistors: r a = 5k and r b = 95.3k yields an output voltage of 24.072v. the power dissipation on the top side mosfet can be easily estimated. choosing a vishay si7848bdp mos - fet results in: r ds(on) = 0.012, c miller = 150pf. at maximum input voltage with t (estimated) = 50c: p main = (24v ? 12v) 24v (12v) 2 ? (4a) 2 ? 1 + (0.005)(50 c ? 25 c) [ ] ? 0.012 + (1.7)(24v) 3 4a 12v (150pf)(350khz) = 0.84w c out is chosen to filter the square current in the output. the maximum output current peak is: i out(peak) = 8 ? 1 + 31% 2 ? ? ? ? ? ? = 9.3a a low esr (5m) capacitor is suggested. this capacitor will limit output voltage ripple to 46.5mv (assuming esr dominates the ripple). pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 6. figure 7 illustrates the current waveforms present in the synchronous regulator operating in the continuous mode. check the following in your layout: 1. put the bottom n-channel mosfet mbot and the top n-channel mosfet mtop1 in one compact area with c out . 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the path formed by the bottom n-channel mosfet and the capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the source terminals of the bottom mosfets. 3. does the ltc3769 vfb pins resistive divider connect to the (+) terminal of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground and placed close to the vfb pin. the feedback resistor connections should not be along the high cur - rent input feeds from the input capacitor(s). 4. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers cur - rent peaks. an additional 1f ceramic capacitor placed immediately next to the int v cc and gnd pins can help improve noise performance substantially. ltc3769 3769f 25 for more information www.linear.com/ltc3769 a pplica t ions i n f or m a t ion figure 6. recommended printed circuit layout diagram figure 7. branch current waveforms sense + sense ? pgood v pullup v in v out sw tg boost bg f in c b m1 m2 gnd 3769 f06 l1 r sense vbias gnd ltc3769 freq ovmode pllin/mode run vfb ith ss intv cc + + r l l1 sw r sense v out c out 3769 f07 v in c in r in bold lines indicate high switching current. keep lines to a minimum length ltc3769 3769f 26 for more information www.linear.com/ltc3769 a pplica t ions i n f or m a t ion 6. keep the switching node (sw), top gate node (tg) and boost node (boost) away from sensitive small-signal nodes. all of these nodes have very large and fast moving signals and, therefore, should be kept on the output side of the ltc3769 and occupy a minimal pc trace area. 7. use a modified star ground technique: a low imped - ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the gnd pins of the ic. pc board layout debugging it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. moni - tor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be main - tained over the input voltage range down to dropout and until the output load drops below the low current opera - tion threshold typically 10% of the maximum designed current level in burst mode operation. t he duty cycle percentage should be maintained from cycle to cycle in a well designed, low noise pcb implementa - tion. variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensa - tion of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. reduce v in from its nominal level to verify operation with high duty cycle. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. an embarrassing problem which can be missed in an oth - erwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hook-up will still be maintained, but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry, the regulator will still maintain control of the output voltage. ltc3769 3769f 27 for more information www.linear.com/ltc3769 typical a pplica t ions figure 8. high efficiency 24v boost converter figure 9. high efficiency 28v boost converter sense + sense ? tg c b 0.1f c itha 220pf ltc3769 c ss 0.1f c ith 15nf c in 22f mtop mbot d c int 4.7f 3769 f09 v out 28v 4a* v in 5v to 28v r sense 4m l 3.3h boost sw vbias bg gnd pgood intv cc vfb ith ss r a 12.1k 100k r ith 8.66k r s 261k freq run ovmode extv cc pllin/mode c outa 22f 4 c outb 150f + c in , c outa : tdk c4532x7r1h685k c outb : suncon 63ce220kx d: bas140w l: pulse pa1494.362nl mbot, mtop: renesas hat2169h *when v in < 8v, maximum load current available is reduced. when v in > 28v, v out follows v in . i lim sense + sense ? tg c b 0.1f c itha 100pf ltc3769 c ss 0.1f c ith 15nf c in 22f mtop mbot d c int 4.7f 3769 f08 v out 24v 5a* v in 5v to 24v r sense 4m l 3.3h boost sw vbias bg gnd pgood intv cc vfb ith ss r a 12.1k 100k r ith 12.1k r s 232k c in , c outa : tdk c4532x5r1e226m c outb : suncon 35hvh150m d: bas140w l: pulse pa1494.362nl mbot, mtop: renesas rjk0452, rjk0453 *when v in < 8v, maximum load current available is reduced. when v in > 24v, v out follows v in . freq run ovmode extv cc pllin/mode c outa 22f 4 c outb 150f + i lim ltc3769 3769f 28 for more information www.linear.com/ltc3769 figure 10. high efficiency 10v boost converter typical a pplica t ions figure 11. high efficiency 24v boost converter with inductor dcr current sensing sense + sense ? tg c b 0.1f c itha 820pf ltc3769 c ss 0.1f c ith 10nf c ina 10f 2 mbot mtop d c int 4.7f 3769 f10 v out * 10v 5a v in 5v to 60v start-up voltage operates through transients down to 2.3v l 1.3h boost sw vbias bg gnd pllin/mode pgood intv cc vfb ith ss r a 64.9k 100k r ith 4.75k r b 475k freq run ovmode extv cc c outa 10f 3 r sense 2m c outb 56f 2 + c inb 50f 2 + l: wrth 7443551130 mbot, mtop: infineon bsc028n06l53 d: bas170w *when v in > 10v, v out follows v in . c ina , c outa : grm32er71j106ka12l c inb , c outb : suncon 63hvh56m i lim sense + sense ? tg c itha 220pf c b 0.1f ltc3769 c ss 0.1f c ith 15nf c in 22f mbot mtop d c int 4.7f 3769 f11a v out 24v* 4a v in 8v to 24v r s2 53.6k 1% c1 0.1f l 10.2h boost sw vbias bg gnd pllin/mode pgood intv cc vfb ith ss r a 12.1k 100k r ith 8.66k r b 232k freq run ovmode extv cc c outa 22f 4 c outb 220f + c1: tdk c1005x7r1c104k c in , c outa : tdk c4532x5r1e226m c outb : suncon, 50ce220ax l: pulse pa2050.103nl mbot, mtop: renesas rjk0305 d: infineon bas140w r s1 26.1k 1% 41.2k i lim output current (a) 3210 94 efficiency (%) 96 98 4 5 6 3769 f11b 92 90 88 86 100 v in = 12v v in = 9v v in = 6v ltc3769 3769f 29 for more information www.linear.com/ltc3769 figure 12. low i q nonsynchronous 24v/2a boost converter typical a pplica t ions figure 13. low i q 24v out sepic converter sense + sense ? tg c itha 100pf ltc3769 c ss 0.1f c ith 10nf c in 10f 2 mbot d c int 4.7f 3769 f12 v out 24v* 2a v in 5v to 60v r sense 6m l 6.8h boost sw vbias bg gnd pgood intv cc i lim vfb ith ss 12.1k 1% 100k r ith 24.9k 232k 1% freq run pllin/mode ovmode extv cc c outa 10f c outb 56f 2 + c in , c outa : murata grm32er71j106ka12l c outb : suncon 63hvh56m d: diodes inc b360 l: coilcraft xal1010 6.8h mbot: infineon bsc100no6ls *when v in > 24v, v out follows v in . 47.5k sense + sense ? tg 100pf ltc3769 0.1f 15nf 4.7f 3 33f m1 4.7f d1 (4) 3769 f13 v out 24v 2.5a v in 18v to 32v 4m l1 sw vbias bg intv cc 4.7f gnd boost vfb ith ss 12.1k 12.1k 232k freq run ilim ovmode extv cc pllin/mode 4.7f 5 l1: coiltronics, versapac vph5-0067-r d1: central semiconductor, cmsh5-60 m1: infineon bsc0281106ls3 ? l1 ? + 220f 2 + ltc3769 3769f 30 for more information www.linear.com/ltc3769 p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2423 1 2 bottom view?exposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf24) qfn 0105 rev b recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697 rev b) ltc3769 3769f 31 for more information www.linear.com/ltc3769 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. fe20 (ca) tssop rev k 0913 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 detail a detail a 111214 13 6.40 ? 6.60* (.252 ? .260) 4.95 (.195) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 6.07 (.239) 6.07 (.239) 4.95 (.195) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc 1.98 (.078) ref fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev k) exposed pad variation ca 0.56 (.022) ref detail a is the part of the lead frame feature for reference only no measurement purpose ltc3769 3769f 32 for more information www.linear.com/ltc3769 ? linear technology corporation 2014 lt 0714 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3769 r ela t e d p ar t s typical a pplica t ion part number description comments ltc3784 2-phase single output synchronous boost controller 4.5v v in 60v, v out up to 60v, 50khz to 900khz, 4mm 5mm qfn-28 and ssop-28 packages ltc3788/ltc3788-1 multiphase, dual output synchronous step-up controller 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, 50khz to 900khz fixed operating frequency, 5mm 5mm qfn-32, ssop-28 ltc3787 2-phase single output synchronous boost controller 4.5v v in 38v, v out up to 60v, 50khz to 900khz, 4mm 5mm qfn-28 and ssop-28 packages ltc3786 low i q synchronous step-up controller 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, 50khz to 900khz fixed operating frequency, 3mm 3mm qfn-32, msop-16e ltc3862/ltc3862-1/ ltc3862-2 multiphase, dual channel single output current mode step-up dc/dc controller 4v v in 36v, 5v or 10v gate drive, 75khz to 500khz fixed operating frequency, ssop-24, tssop-24, 5mm 5mm qfn-24 lt3757/lt3758 boost, flyback, sepic and inverting controller 2.9v v in 40v/100v, 100khz to 1mhz fixed operating frequency, 3mm 3mm dfn-10 and msop-10e ltc3859al low i q , triple output buck/buck/boost synchronous dc/dc controller all outputs remain in regulation through cold crank, 4.5v (down to 2.5v after start-up) v in 38v, v out(bucks) up to 24v, v out(boost) up to 60v, i q = 28a ltc3789 high efficiency synchronous 4-switch buck-boost dc/dc controller 4v v in 38v, 0.8v v out 38v, 4mm 5mm qfn-28 and ssop-28 lt8705 80v v in and v out synchronous 4-switch buck-boost dc/dc controller v in range: 2.8v (need extv cc > 6.4v) to 80v, v out range: 1.3v to 80v, four regulation loops ltc3890/ltc3890-1/ ltc3890-2/ltc3890-3 60v, low i q , dual 2-phase synchronous step-down dc/dc controller phase-lockable fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a figure 14. high efficiency 48v/2.5a boost converter sense + sense ? tg c b 0.1f c itha 100pf ltc3769 c ss 0.1f c ith 15nf c in 4.7f 3 mtop mbot d c int 4.7f 3769 f14 v out 48v 2.5a* v out follows v in when v in > 48v v in 5v to 55v r sense 3m l 10h boost sw vbias bg gnd pgnd pgood intv cc vfb ith ss r a 12.1k 100k 100k r ith 15k r b 475k freq run pllin/mode ovmode extv cc c outa 4.7f 5 c outb 33f 2 + c in , c outa : tdk c3225x7s2a475m c outb : suncon 63hvh33m d: bas170w l: ser2918h-103 mbot, mtop: bsc028n06l53 *when v in < 13v, maximum load current available is reduced. 30.1k ltc3769 3769f |
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